The present invention relates to an imaging apparatus for imaging multiple subjects with a plurality of solid-state imaging devices and synthesizing image signals of multiple systems that are obtained from the solid-state imaging devices.
An imaging apparatus, such as a digital still camera, may employ a plurality of solid-state imaging devices to simultaneously image different subjects. Such an imaging device synthesizes image signals of multiple systems that are obtained from the solid-state imaging devices and, for example, displays a plurality of reproduced images on a single image display screen.
FIG. 1 is a block diagram of a prior art imaging apparatus 20 employing a plurality of solid-state imaging devices. To generate an image, or take pictures, of two subjects, the imaging apparatus 20 has first and second imaging devices 20a, 20b. A memory controller 9 controls the output of the first and second imaging devices 20a, 20b. 
The first imaging device 20a, which defines a first imaging system, includes a first solid-state imaging device, or charge-coupled device (CCD) 1a, a first boost circuit 2a, a first CCD driver circuit 3a, a first timing control circuit 4a, a first analog signal processing circuit 5a, a first A/D conversion circuit 6a, a first digital signal processing circuit 7a, and a first memory 8a. The first CCD 1a includes a matrix of light receiving pixels and accumulates information charges generated in accordance with a received first subject image in the light receiving pixels. The first CCD 1a has a vertical overflow drain structure and discharges the information charges accumulated in each light receiving pixel toward a substrate. The vertical overflow drain structure causes excessive information charges generated in the light receiving pixels to be absorbed by the substrate.
The first boost circuit 2a boosts input power supply voltage Vd (not shown) to generate a boosted voltage and supplies the boosted voltage to the first CCD driver circuit 3a. The first CCD driver circuit 3a uses the boosted voltage to generate a plurality of clock pulses and provides the clock pulses to the first CCD 1a. The clock pulses are generated in accordance with various timing signals, which are provided from a first timing control circuit 4a. An image signal Y(t), which is in accordance with the charge amount of the information charges accumulated in each light receiving pixel, is retrieved from the first CCD 1a in units of single pixels.
The first timing control circuit 4a includes a plurality of counters (not shown), which count a reference clock signal CK that has a fixed cycle, and divides the reference clock signal CK to generate a vertical synchronizing signal VD and a horizontal synchronizing signal. The first timing control circuit 4a generates various timing signals, which are provided to the first CCD driver circuit 3a, at timings synchronized with the vertical and horizontal synchronizing signals VD, HD. The first CCD 1agenerates an image signal Ya(t) for each line at a timing synchronized with the horizontal synchronizing signal HD and generates an image signal Ya(t) for each image display screen at a timing synchronized with the vertical synchronizing signal VD. The generated image signal Y(t) is provided to the first analog signal processing circuit 5a. 
The first analog signal processing circuit 5a receives the image signal Ya(t) from the first CCD 1a and performs analog signal processing, such as a correlated double sampling (CDS) process and an automatic gain control (AGC) process, on the image signal Ya(t). In the CDS process, the image signal Ya(t), which repeats a reset level and a signal level, is clamped at the reset level. Subsequently, the signal level is extracted from the image signal Ya(t) and an image signal having a continuous signal level is generated. In the AGC process, the image signals retrieved in the CDS process are integrated in units of single image display screens or single vertical scan terms. The gain is feedback-controlled so that the integrated data is included in a predetermined range. The first A/D converter 6a receives the image signal Ya(t) from the first analog signal processing circuit 5a, standardizes the image signal Ya(t) in synchronism with the output timing of the first CCD 1a, and generates first digital image data Ya(n). The first digital image data Ya(n) is provided to the first digital signal processing circuit 7a. 
The first digital signal processing circuit 7a performs processes such as color separation and a matrix operation on the first digital image data Ya(n) to generate image data Y′(n), which includes luminance data and chrominance data. The first digital signal processing circuit 7a includes an exposure controller and a white balance controller and performs exposure control, which controls the exposure state of the first CCD 1a, and a white balance correction process, which adjusts the white balance of the image signal Y(t).
The first memory 8a is a frame memory and stores the luminance data and the chrominance data from the first digital signal processing circuit 7a in response to a write command from the memory controller 9.
The second imaging device 20b, which defines a second imaging system, includes a second solid-state imaging device, or charge-coupled device (CCD) 1b, a second boost circuit 2b, a second CCD driver circuit 3b, a second timing control circuit 4b, a second analog signal processing circuit 5b, a second A/D conversion circuit 6b, a second digital signal processing circuit 7b, and a second memory 8b. The circuits of the second imaging device 20b correspond to the circuits of the first imaging device 20a and perform the same processes on a second image signal generated by the second CCD 1b. 
The memory controller 9 controls the read timing of the first and second image data so that the image generated by the first imaging device 20a and the image generated by the second imaging device 20b are reproduced on a single image display screen. For example, referring to FIG. 2A, a single image display screen is divided into two sections. A first image A, which is generated by the first imaging device 20a, is shown in one section, and a second image B, which is generated by the second imaging device 20b, is shown in the other section. In this case, the first image data Ya(n), which corresponds to the first image A, and the second image data Yb(n), which corresponds to the second image B, are respectively retrieved from the first and second memories 8a, 8b. Afterward, the two pieces of image data are synthesized in accordance with the display mode of the image display screen.
In FIG. 2B, the first image A is mainly shown on the image display screen. The lower left quarter of the image display screen shows the second image B in a miniaturized state. In this case, the first image data Ya(n) that corresponds to the upper half of the image display screen is read from the first memory 8a. Then, the first image data Ya(n) and the second image data Yb(n) corresponding to the lower half of the image display screen are read from the first and second memories 8a, 8b. In this state, to show the second image B in the allocated section of the image display screen, the image data of a single image is read from the second memory 8b and compressed to one forth. The first image data Ya(n) and the compressed image data Yb(n) are then synthesized to simultaneously show the first image A and the second image B, which is miniaturized by one forth, on the same image display screen.
The conventional imaging apparatus 20 includes may circuits, such as the CCDs, the drive circuits, the timing control circuits, and the signal processing circuits. As a result, the imaging apparatus 20 has a large scale and consumes a large amount of power. Accordingly, circuits other than the CCDs may be used commonly, or combined, to reduce the circuit scale of the imaging apparatus. There are many possible combinations. However, when circuits are combined, the capacity of the imaging apparatus may decrease. For example, when the drive system is combined, plural CCDs may not be driven simultaneously. This would decrease the frame rate of each CCD.